Wafer-Level Testing and Test During Burn-In for Integrated Circuits

by Sudarshan Bahukudumbi and Krishnendu Chakrabarty

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Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias... This description may be from another edition of this product.

Format:Hardcover

Language:English

ISBN:1596939893

ISBN13:9781596939899

Release Date:February 2010

Publisher:Artech House Publishers

Length:198 Pages

Weight:0.95 lbs.

Dimensions:0.7" x 6.2" x 9.1"

Related Subjects

Engineering Technology

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Wafer-Level Testing and Test During Burn-In for Integrated Circuits

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