VHDL: Coding and Logic Synthesis with Synopsys

I have four VHDL books right now and this is the best. The other books teach you the entire language set, which is nice, but they fail to mention that only a segment of the language is synthesizable. This book does a great job teaching you how to program with effective VHDL code period. This is very important because it can save you countless hours of code rewriting.

I agree with previous author. This book won't let you sleep like the "designer's guide to VHDL" will. I strongly recommend reading this book and then read another excellent book ""Digital Systems Design with VHDL and Synthesis" by "K.C. Chang".However, this book still has weakness, it lacks some detailed info about the sysnthesis tool, such like what is wireload model. Knowing those in a little more detail should help the design in getting better result. Also I am not sure what is the point spending more than 100 pages with all the Appendix such like a list of the std_logic_1164 library and the EDIF files. I would rather having more detail info about the synthesis theory than those listing or take out the listings and cut the price down... .

I bought this book together with the "Designer's Guide to VHDL", And I decided to read the later first. One week ago, I found out I was making a big mistake.This book is wonderful, The author put in clear and necessary information and his experience to make the book thick, rather than putting in verbose explanations. When you read this book, you save your time and get better understand of the language, and you can start writing your own code very soon.I love this book, and it doesn't make me sleepy like the "designer's guide to vhdl" did.

This book is highly recommended for all the students and engineers. It explains synthesis in detail with examples showing the reader how to use Synopsys commands to optimize synthesized designs. Besided that, figures and explanations are also included throughout. So, keep it one for yourself!

The book is very well written and easy to understand. It has a lot of real life design examples with the code, testbench, simulation results and synthesis tweaks. I would recommend this book to anyone using Synopsys's DC or anyone who wants to write synthesizable VHDL. I especially like the portion of the book which shows all the different methods that can be used to tweak a design in synthesis.A book that deserves a good spot in my collection of technical design books.