Veriloga (R) QuickStart

I have a VHDL background and this book was recommended to me. It made a smoooth transition into verilog. I read the book globally and then kept the book as a reference on my desk. If I needed something specific like file I/O and generating vectors, I used the example as a template to complete my verification. Also it helped to organize my files, like having one verification environment and easily plugging in tests by use of common tasks. Currently I am using Verilog and System Verilog, this book is still used regularly.

I was lucky to have James Lee class at ucsc/ca. This book willbe very useful for all reader from beginer to practical expert.

The book provides a good resource for those designers that already know Verilog and wish to have coding tips for simulation testbenches. It is learn-by-example format, and is updated to include the '99 verilog standard. The book is well laid out, meaning that from the index it is easy to find a relevant coding example. I also bought "A designers guide to VHDL" Peter J. Ashendon which is a language reference for VHDL by example.