Low Power Latch Designs in Subthreshold Region

by Abhilasha Choudhary, Krishna Sharma, Tripti Sharma

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In recent years, low power design has become one of the focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers.... This description may be from another edition of this product.

Format:Paperback

Language:English

ISBN:365916061X

ISBN13:9783659160615

Release Date:June 2012

Publisher:LAP Lambert Academic Publishing

Length:80 Pages

Weight:0.28 lbs.

Dimensions:0.2" x 6.0" x 9.0"

Related Subjects

Engineering Technology

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Low Power Latch Designs in Subthreshold Region

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