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Paperback High-Level Verification: Methods and Tools for Verification of System-Level Designs Book
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ISBN: 149390101X

ISBN13: 9781493901012

High-Level Verification: Methods and Tools for Verification of System-Level Designs

by , , , et al.
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Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of...

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Computers Computers & Technology Engineering Technology

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