High Level Synthesis of Asics Under Timing and Synchronization Constraints

by David C. Ku and Giovanni de Micheli

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Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting...

Format:Paperback

Language:English

ISBN:1441951296

ISBN13:9781441951298

Release Date:November 2010

Publisher:Springer

Length:294 Pages

Weight:0.97 lbs.

Dimensions:0.7" x 6.1" x 9.2"

Related Subjects

Computers Computers & Technology Electrical & Electronics Engineering Technology

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High Level Synthesis of Asics Under Timing and Synchronization Constraints

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