High-Level Estimation and Exploration of Reliability for Multi-Processor System-On-Chip

by Anupam Chattopadhyay and Zheng Wang

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This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

Format:Paperback

Language:English

ISBN:9811093210

ISBN13:9789811093210

Release Date:May 2018

Publisher:Springer

Length:197 Pages

Weight:0.69 lbs.

Dimensions:0.5" x 6.1" x 9.2"

Related Subjects

Computers Computers & Technology Engineering Technology

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High-Level Estimation and Exploration of Reliability for Multi-Processor System-On-Chip

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