A VHDL Synthesis Primer
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Book Overview
Here is the latest book from the Bell Labs VHDL expert. This is a primer for anyone learning circuit synthesis using VDHDL, an IEEE standard design and simulation language. A VHDL Synthesis Primer starts by explaining synthesis basics, then shows details of how each VHDL construct gets translated into hardware. Modeling guidelines are provided to help improve synthesis results.
Format:Hardcover
Language:English
ISBN:0965039102
ISBN13:9780965039109
Release Date:January 1996
Publisher:Star Galaxy Pub.
Length:238 Pages
Weight:1.11 lbs.
Dimensions:0.8" x 6.3" x 9.3"
Customer Reviews
2 ratings
Very informative
Published by Thriftbooks.com User , 23 years ago
It is a well written book , covering all aspects of VHDL.This would be a must buy for students who would liketo start a career in VLSI, and also to those designerswho are not so familier with synthesis aspects of VHDL
concise & practical
Published by Thriftbooks.com User , 24 years ago
In the modeling of digital logic with VHDL, sometimes you're wondering what difference between signals and variables in your code, what the literals of integer type really means in hardware, and why the signed and unsigned types are so convenient to use in many situations. Don't worry. J. Bhasker tells you what you want to know by good examples. It's useful both for beginners and practicing engineers.
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