- Logic Minimization Algorithms for VLSI Synthesis (The International Series in Engineering and Computer Science)
- Timed Boolean Functions: A Unified Formalism for Exact Timing Analysis (The International Series in Engineering and Computer Science)
- Logic Synthesis for Field-Programmable Gate Arrays (The Springer International Series in Engineering and Computer Science)
- Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics
- Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications (The Springer International Series in Engineering and Computer Science)